In the fabrication of static random access memories (SRAMs) as well as various other types of integrated circuits, it is known construct both P-channel and N-channel MOS transistors in a silicon wafer and to electrically isolate these transistors by the use of N-wells and P-wells, respectively. CMOS integrated circuits offer a more powerful circuit operation than either N-channel or P-channel circuits alone. This factor, combined with the lower power consumption and increased speed, has made CMOS the favored technology for the manufacture of microprocessors and memory devices. It is also well known to construct bipolar transistors in these integrated circuits in order to provide added circuit flexibility and current drive capability to these integrated circuits.
Earlier processes used for manufacturing these BiCMOS integrated circuits utilized separate and dedicated photoresist masking steps to form CMOS transistors on the one hand and the bipolar transistors on the other hand in order to provide the necessary processing isolation required in defining, doping, and making electrical connections to these different types of transistors. Typically, the areas of the silicon wafer in which the CMOS transistors were formed were subjected to a specific series of photolithographic masking and etching steps using photoresist masks to implant and then drive in dopant impurities into the CMOS transistor regions. Another completely different series of photolithographic masking and etching steps were then used for masking the area of the silicon wafer in which the bipolar transistor regions were formed using ion implantation and drive in diffusion processes well known in the art.
In order to reduce the member of processing steps required in the above prior art BiCMOS process, there has been developed a new and improved BiCMOS process wherein the bipolar transistors formed in the silicon wafer do not require dedicated photoresist masking and etching processes. This feature in turn thereby significantly reduces the total number of individual process steps and reticles required in the overall integrated circuit process flow. This new and improved process is disclosed and claimed in U.S. Pat. No. 4,987,089 issued to Ceredig Roberts, assigned to the present assignee and incorporated herein by reference.